module ysyx_22040213_dataram (
	  input rst,
	  input clk,
	  
	  // ram enable
	  input dataram_req,
	  input wr,
	  input [2:0] size,
	  input [63:0] addr,
	  input [7:0] wstrb,
	  input [63:0] wdata,
	   
	  output reg addr_ok,
	  output reg data_ok,
	  output reg [63:0] rdata
);

	import "DPI-C" function void mpmem_read(input longint raddr, output longint rdata);
	import "DPI-C" function void mpmem_write(input longint waddr, input longint wdata, input byte wmask);
	always @(*) begin
		if(!wr)begin
			addr_ok = 1'b1;
			if(dataram_req)begin
			  mpmem_read(addr, o_mem_data);
			end
		end
		else if(wr)begin
			addr_ok = 1'b1;
			if(dataram_req)begin
			  o_mem_data = 0;
	      		  case(wstrb)
				8'h01 : mpmem_write(addr, wdata, 8'h01);//sb
				8'h03 : mpmem_write(addr, wdata, 8'h03);//sh
				8'h0f : mpmem_write(addr, wdata, 8'h0f);//sw
				8'hff : mpmem_write(addr, wdata, 8'hff);//sd 
				default : mpmem_write(addr, wdata, 8'b00000000);
			  endcase
		  	end	  
		end
		else begin
			addr_ok = 1'b0 && |size;
			o_mem_data = 0;
		end
	end

	reg [63:0] o_mem_data;
//	assign data_ok = 1'b1 && |size;
       
//	Reg #(64,64'h0) i0 (clk, !rst, o_mem_data, rdata, !wr && dataram_req);

	always @(posedge clk)begin
		if(rst)begin
		  rdata <= o_mem_data;
	          data_ok <= 1'b0;
		end
		if(dataram_req && !wr)begin
		  rdata <= o_mem_data;
		  data_ok <= 1'b1;
	  	end
		else if(dataram_req && wr)begin
		  rdata <= 0;
		  data_ok <= 1'b1;
	  	end
	end


endmodule
